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ICS T8850處理器卡件
主延遲用于延遲來(lái)自跟隨器重合閘功能的閉合命令的信號的I/P。
該信號在主重合閘功能的死區時(shí)間開(kāi)始時(shí)出現，并在循環(huán)的最后一次重合閘，或在主控成功重合閘后等待時(shí)間結束時(shí)。如果不需要，則設置為“off”（“F”或“False”）。
Mast.noSucc來(lái)自主CB的阻塞信號的I/P。
該信號由“Def.Trip”上升沿觸發(fā)主重合閘功能的輸出，并在500毫秒的固定時(shí)間。
如果不需要，則設置為“off”（“F”或“False”）。延遲FLWR。
只要主斷路器尚未完成其自動(dòng)重合閘循環(huán)，就發(fā)出信號延遲跟隨器CB。
信號在主AR死區時(shí)間開(kāi)始時(shí)拾取，并且由“Def”的上升沿重置。跳閘輸出或“關(guān)閉CB”輸出在時(shí)間“tClose”后的下降沿。Blk.toFlwr
只要主CB不成功。
該信號的偏移與“Def.Trip”相同
輸出雙重邏輯
CB2就緒當CB2準備就緒時(shí)，由CB2信號激勵的I/P（打開(kāi)/關(guān)閉/打開(kāi)）。
如果不需要或未安裝，則設置為“關(guān)閉”（“F”或“假”）。
I/P邏輯：“CB就緒”或“CB2就緒”在雙工方案中，自動(dòng)重合閘循環(huán)由激活的“CB就緒”或“CB2就緒”I/P啟用。該輸入的復位在內部延遲100ms。
CO就緒2當CB2準備就緒時(shí)，由CB2信號激勵的I/P關(guān)閉/打開(kāi)操作。
設置為“開(kāi)”（“T”或“真”），如果不需要，則不安裝和“死”不使用第2行。
用于啟用關(guān)閉命令的I/P邏輯：[（“同步檢查2”）和“CO就緒2”）或“死線(xiàn)2”或“ExtSCBypas”]。
CB2公開(kāi)賽當CB2打開(kāi)時(shí)，由來(lái)自CB2的信號激勵的I/P。
如果不需要，則設置為“on”（“T”或“True”）。觀(guān)察在雙工方案中為雙工邏輯提供的信息
MasterDelay
I/P for a signal delaying the closing command from the follower reclosure function.
This signal picks up when the dead time of the master reclosure function starts and is reset either by a new trip after the
last reclosure of the cycle or at the end of the wait time following successful reclosure by the master.
Set to ‘off’ (‘F’ or ‘False’), if not needed.
Mast.noSucc
I/P for a blocking signal from the master CB.
This signal is triggered by the rising edge of the ‘Def.Trip’
output from the master reclosure function and resets after a
fixed time of 500 ms.
Set to ‘off’ (‘F’ or ‘False’), if not needed.
DelayFlwr.
Signal to delay the follower CB for as long as the master circuit-breaker has not completed its auto-reclosure cycle.
The signal picks up at the start of master AR dead time and
is reset either by the rising edge of the ‘Def.Trip’ output or the
falling edge of the ‘Close CB’ output after the time ‘tClose’.
Blk.toFlwr
Signal to block the follower CB as long as reclosure of the
master CB is unsuccessful.
The excursion of this signal is the same as for the ‘Def.Trip’
output.DUPLEX LOGIC
CB2 Ready
I/P excited by a signal from CB2 when it is ready
(open/close/open).
Set to ‘off’ (‘F’ or ‘False’), if not needed or not fitted.
I/P logic: ‘CB ready’ OR ‘CB2 ready'
In a duplex scheme, the auto-reclosure cycle is enabled either by an active ‘CB ready’ or ‘CB2 ready’ I/P.
Resetting of this input is delayed internally by 100 ms.
CO Ready 2
I/P excited by a signal from CB2 when it is ready for a
close/open operation.
Set to ‘on’ (‘T’ or ‘True’), if not needed, not fitted and ‘Dead
line 2’ is not used.
I/P logic for enabling the close command:: [(‘synchrocheck2’
AND ‘CO Ready 2’) OR ‘Dead line 2’ OR ‘ExtSCBypas'].
CB2 open
I/P excited by a signal from CB2 when it is open.
Set to ‘on’ (‘T’ or ‘True’), if not needed. Observe the information given for the duplex logic in a duplex scheme
