產(chǎn)品內容介紹
5X00502G01數字量輸入卡件
12-PULSE LOGIC功能塊參數（S13/16）。如果兩個(gè)轉換器中的實(shí)際電流沒(méi)有并聯(lián)下降，并且沒(méi)有預期下降，那么延遲時(shí)間在REV_delay時(shí)間結束后開(kāi)始，以使系統能夠自我糾正。在此期間，反轉被阻止。延遲時(shí)間以倍數定義循環(huán)數（參見(jiàn)REV_DELAY）。橋接器反轉將獨立于另一個(gè)轉換器的實(shí)際電流信號（如果時(shí)間已過(guò)）。功能是獨立于控制模式（6或12脈沖或DCF模式）。此參數必須具有主控形狀和從動(dòng)形狀的設置相同。（S21.232中HL較高）FREV_DELAY12-PULSE LOGIC功能塊參數（S13/16）。
當電流參考極性反轉時(shí)，此延遲時(shí)間開(kāi)始。如果電橋反轉成功，此延遲時(shí)間被重置。如果橋接器反轉失敗經(jīng)過(guò)該時(shí)間后，將顯示故障消息F65。
逆轉可能失敗，因為一個(gè)轉換器交換了橋接器或轉換器交叉交換橋接器其他的東西。最后，兩個(gè)轉換器的電流不會(huì )增加橋該延遲時(shí)間定義為循環(huán)的倍數（參見(jiàn)REV_delay）。功能獨立于控制模式（6或12脈沖或DCF模式）。此參數必須在主控形狀和從動(dòng)形狀上具有相同的設置，并且必須大于REV_DELAY和REV_GAP加上安全裕度。（S21.232中HL較高）
12-PULSE LOGIC功能塊的輸入（S13/16）。
指向模擬硬件輸入的指針。默認情況下，模擬輸入2已連接。
在作為12脈沖主控器工作的轉換器上，實(shí)際電流信號從SLAVE必須連接到硬件并傳輸到此輸入。
在作為12脈沖SLAVE工作的轉換器上，實(shí)際電流信號從MASTER必須連接到硬件并傳輸到此輸入。傳遞到此指針的信號在插頭連接器X18:11處輸出通過(guò)電纜傳輸的信號與連接的信號相反。這互連可用于故障安全電路。它可以在所有模式下工作。
根據接線(xiàn)圖，應進(jìn)行以下互連：-如果使用無(wú)冗余的12脈沖系統（見(jiàn)INHIB_LOGIC）：
-將此輸入連接到兩個(gè)轉換器的RDY_ON（10901），主轉換器和跟隨者
-如果使用12脈沖冗余系統（見(jiàn)BC-LOGIC）：
-將此輸入連接到兩個(gè)轉換器的BC_NOT_ZERO（13621），主轉換器和追隨者
Parameter of 12-PULSE LOGIC-function block (S13/16 ).
If the actual current doesn′t go down in parallel and as expected in both converters this delay time is started when the time of REV_DELAY has elapsed to enable the system to correct itself. During this time the reversal is blocked. The delay time is defined in multiples of cycles (see REV_DELAY). The bridge reversal will be performed independent of the actual current signal of the other converter, if the time has elapsed. The function is independent of the control mode (6- or 12-pulse or DCF mode). This parameter must have the same setting at the Master and the Follower. (higher HL in S21.232)FREV_DELAY Parameter of 12-PULSE LOGIC-function block (S13/16 ). This delay time is started when the polarity of the current reference is inverted. In case the bridge reversal is successful this delay time is reset. In case the bridge reversal failed the fault message F65 is displayed when the time is elapsed. A reversal may fail because only one converter swapped the bridge or the converters swapped bridges crosswise or something else. At the end the current is not increased at both converters with the same bridge. This delay time is defined in multiples of cycles (see REV_DELAY). ). The function is independent of the control mode (6- or 12-pulse or DCF mode). This parameter must have the same setting at the Master and the Follower and must be greater than the sum of REV_DELAY and REV_GAP plus a safety margin. (higher HL in S21.232)
Input of 12-PULSE LOGIC-function block
(S13/16 ). Pointer to an analog hardware input. In default condition the analog input 2 is connected. At converters working as a 12 pulse MASTER the actual current signal taken out of the SLAVE has to be connected to the hardware and transferred to this input. At converters working as a 12 pulse SLAVE the actual current signal taken out of the MASTER has to be connected to the hardware and transferred to this input.The signal passed to this pointer is outputted at Plug Connector X18:11. The logic level of the signal transferred via the cable is inverted compared the one connected to. This interconnection can be used for a fail-safe circuit. It is operative in all modes. Based on the connection diagram this interconnection should be done: - in case a 12 pulse system without redundancy is in use (see INHIB_LOGIC): - connect this input to RDY_ON (10901) at both converters, the Master and the Follower - in case a 12 pulse system with redundancy is in use (see BC-LOGIC): - connect this input to BC_NOT_ZERO (13621) at both converters, the Master and the Follower
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