RELIANCE 45C271內存擴展模塊
當設置為邏輯1（1）時(shí)，啟用跟蹤。該位必須設置為邏輯1，以允許外部寄存器更新。Ipsw-第6位中斷開(kāi)關(guān)-該位用于在日間時(shí)間報警和看門(mén)狗報警之間切換中斷輸出。當設置為邏輯零（0）時(shí)，中斷輸出來(lái)自看門(mén)狗報警。當設置為邏輯一（1）時(shí)，中斷輸出來(lái)自日時(shí)報警。Ibh/lo-保留位5-該位應設置為邏輯低（0）。Pu/lvl—第4位中斷脈沖模式或電平模式—該位確定中斷輸出是作為脈沖還是電平輸出。當設置為邏輯零（0）時(shí)，中斷輸出將為一個(gè)電平。當設置為邏輯1（1）時(shí)，中斷輸出將是一個(gè)脈沖。在脈沖模式下，中斷輸出將吸收電流至少3毫秒。該位應設置為邏輯1（1）。Wam-位3看門(mén)狗報警掩碼-當Ipsw（位6，中斷開(kāi)關(guān)）設置為邏輯零（0）時(shí)，啟用/禁用看門(mén)狗報警以中斷輸出。當設置為邏輯零（0）時(shí)，將啟用看門(mén)狗報警中斷輸出。當設置為邏輯1（1）時(shí)，看門(mén)狗報警中斷輸出將被禁用。
When set to a logic one (1), tracking is enabled. This bit must be set to a logic one (1) to allow the external register to be updated. Ipsw - Bit 6 Interrupt Switch - This bit toggles the Interrupt Output between the Time of Day Alarm and the Watchdog Alarm. When set to a logic zero (0), the Interrupt Output is from the Watchdog Alarm. When set to a logic one (1), the Interrupt Output is from the Time of Day Alarm. Ibh/lo - Bit 5 Reserved - This bit should be set to a logic low (0). Pu/lvl - Bit 4 Interrupt Pulse Mode or Level Mode - This bit determines whether the Interrupt Output will output as a pulse or a level. When set to a logic zero (0), Interrupt Output will be a level. When set to a logic one (1), Interrupt Output will be a pulse. In pulse mode the Interrupt Output will sink current for a minimum of 3 ms. This bit should be set to a logic one (1). Wam - Bit 3 Watchdog Alarm Mask - Enables/Disables the Watchdog Alarm to Interrupt Output when Ipsw (Bit 6, Interrupt Switch) is set to logic zero (0). When set to a logic zero (0), Watchdog Alarm Interrupt Output will be enabled. When set to a logic one (1), Watchdog Alarm Interrupt Output will be disabled.
