EMERSON 5X00105G07 PLC模塊
計時(shí)器控制狀態(tài)寄存器1（TCSR1）計時(shí)器通過(guò)位于BAR2地址偏移0x00處的計時(shí)器控制狀態(tài)暫存器1（TCSR 1）進(jìn)行控制和監控。該寄存器中的位映射如下：每個(gè)定時(shí)器都有一個(gè)獨立選擇的時(shí)鐘源，該時(shí)鐘源由“定時(shí)器x時(shí)鐘選擇”字段中的位模式選擇，如下所示：通過(guò)將“1”寫(xiě)入適當的“定時(shí)器x啟用”字段，可以獨立啟用每個(gè)定時(shí)器。類(lèi)似地，通過(guò)將“1”寫(xiě)入適當的“timer x IRQ Enable”字段，可以獨立啟用每個(gè)計時(shí)器產(chǎn)生的中斷。如果中斷由計時(shí)器產(chǎn)生，則可以通過(guò)讀取“計時(shí)器x引起的IRQ”字段來(lái)確定中斷源。如果字段設置為“1”，則相應的計時(shí)器導致中斷。請注意，多個(gè)計時(shí)器可能會(huì )導致一次中斷。因此，必須讀取所有計時(shí)器的狀態(tài)，以確保識別所有中斷源。
Timer Control Status Register 1 (TCSR1)
The timers are controlled and monitored via the Timer Control Status Register 1
(TCSR1) located at offset 0x00 from the address in BAR2. The mapping of the bits in
this register are as follows:Each timer has an independently selectable clock source which is selected by the bit
pattern in the “Timer x Clock Select” field as follows:Each timer can be independently enabled by writing a “1” to the appropriate “Timer x
Enable” field. Similarly, the generation of interrupts by each timer can be
independently enabled by writing a “1” to the appropriate “Timer x IRQ Enable”
field.
If an interrupt is generated by a timer, the source of the interrupt may be determined
by reading the “Timer x Caused IRQ” fields. If the field is set to “1”, then the
respective timer caused the interrupt. Note that multiple timers can cause a single
interrupt. Therefore, the status of all timers must be read to ensure that all interrupt
sources are recognized.
