EMERSON KJ3201X1-BA1控制器
通過(guò)將“0”寫(xiě)入適當的“timer x Caused IRQ”字段，可以清除特定的定時(shí)器中斷?；蛘?，寫(xiě)入適當的Timer x IRQ Clear（TxIC）寄存器也將清除中斷。使用“Timer x Caused IRQ”（定時(shí)器x引起的IRQ）字段清除中斷時(shí)，請注意，確保使用正確的位掩碼，以免影響其他寄存器設置非常重要。清除中斷的首選方法是使用下面描述的“Timer x IRQ Clear”寄存器。計時(shí)器控制狀態(tài)寄存器2（TCSR2）計時(shí)器也由位于BAR2地址偏移0x04處的計時(shí)器控制狀態(tài)暫存器2（TCSR 2）中的位控制。該寄存器中的位映射如下：“讀鎖存選擇”位用于選擇可編程定時(shí)器的鎖存模式（參見(jiàn)上文“定時(shí)器”部分）。如果該位設置為“0”，則每個(gè)定時(shí)器輸出在讀取其任何一個(gè)地址時(shí)被鎖存。例如，對TMRCCR12寄存器的讀取鎖存計時(shí)器1和2的計數。對TMRCCR3寄存器的讀取鎖存定時(shí)器3的計數。對于這些寄存器中的任何一個(gè)的每次讀取，都會(huì )繼續執行此操作。
A particular timer interrupt can be cleared by writing a “0” to the appropriate “Timer
x Caused IRQ” field. Alternately, a write to the appropriate Timer x IRQ Clear (TxIC)
register will also clear the interrupt. When clearing the interrupt using the “Timer x
Caused IRQ” fields, note that it is very important to ensure that a proper bit mask is
used so that other register settings are not affected. The preferred method for clearing
interrupts is to use the “Timer x IRQ Clear” registers described below.
Timer Control Status Register 2 (TCSR2)
The timers are also controlled by bits in the Timer Control Status Register 2 (TCSR2)
located at offset 0x04 from the address in BAR2. The mapping of the bits in this
register are as follows:The “Read Latch Select” bit is used to select the latching mode of the programmable
timers (See “Timers” section above). If this bit is set to “0”, then each timer output is
latched upon a read of any one of its address. For example, a read to the TMRCCR12
register latches the count of timers 1 and 2. A read to the TMRCCR3 register latches
the count of timer 3. This continues for every read to any one of these registers.
