EMERSON KJ2004X1-BA1遠程接口單元
看門(mén)狗定時(shí)器概述VMIVME-7750提供了一個(gè)可編程看門(mén)狗定時(shí)器（WDT），如果軟件完整性失敗，可以使用它來(lái)重置系統。WDT控制狀態(tài)寄存器（WCSR）WDT由位于BAR2地址偏移0x08處的WDT控制狀況寄存器（WCS）控制和監控。此寄存器中的位映射如下：“WDT超時(shí)選擇”字段用于選擇看門(mén)狗定時(shí)器的超時(shí)值，如下所示：“SERR/RST選擇”位用于選擇WDT是否在本地PCI總線(xiàn)上生成SERR#或系統重置。如果該位設置為“0”，WDT將生成系統重置。否則，WDT將激活本地PCI總線(xiàn)SERR#信號?！癢DT啟用”位用于啟用看門(mén)狗定時(shí)器功能。該位必須設置為“1”，以便看門(mén)狗定時(shí)器工作。請注意，由于復位后所有寄存器都默認為零，因此在復位后看門(mén)狗定時(shí)器始終被禁用。重置后，應用軟件必須重新啟用看門(mén)狗定時(shí)器，以便看門(mén)狗定時(shí)器繼續運行。
Watchdog Timer
General
The VMIVME-7750 provides a programmable Watchdog Timer (WDT) which can be
used to reset the system if software integrity fails.
WDT Control Status Register (WCSR)
The WDT is controlled and monitored by the WDT Control Status Register (WCSR)
which is located at offset 0x08 from the address in BAR2. The mapping of the bits in
this register are as follows:The “WDT Timeout Select” field is used to select the timeout value of the Watchdog
Timer as follows:The “SERR/RST Select” bit is used to select whether the WDT generates an SERR# on
the local PCI bus or a system reset. If this bit is set to “0”, the WDT will generate a
system reset. Otherwise, the WDT will make the local PCI bus SERR# signal active.The “WDT Enable” bit is used to enable the Watchdog Timer function. This bit must
be set to “1” in order for the Watchdog Timer to function. Note that since all registers
default to zero after reset, the Watchdog Timer is always disabled after a reset. The
Watchdog Timer must be re-enabled by the application software after reset in order
for the Watchdog Timer to continue to operate.
