P0926GH冗余總線(xiàn)卡，FOXBORO中文PDF用戶(hù)手冊
SCON狀態(tài)位反映了收割臺J3。連接J3針腳1和2時(shí)，啟用MVME147充當VMEbus系統控制器，然后是SCON= 1. 當J3針腳1和2未連接時(shí)，MVME147為不是VMEbus系統控制器，SCON=0。位1該位允許軟件啟動(dòng)全局重置序列。設置SRESET位將激活主機上的SYSRESET*信號VMEbus，反過(guò)來(lái)重置MVME147。此位清除重置完成后自動(dòng)執行。該位被清除任何重置。
P0926GH冗余總線(xiàn)卡位2將BRDFAIL設置為1會(huì )導致VMEchip嘗試激活VMEbus上的SYSFAIL*信號。GCSR位抑制
全局寄存器1中的SYSFAIL（ISF）使MVME147能夠由于的狀態(tài)，導致SYSFAIL*被激活BRDFAIL。此外，當設置位時(shí)，故障指示燈點(diǎn)亮。（A）PCC的看門(mén)狗超時(shí)也會(huì )點(diǎn)亮故障指示燈。）
該位由任何重置設置。位3 ROBIN位配置VMEbus仲裁模式。ROBIN=1強制循環(huán)模式。ROBIN=0強制優(yōu)先級模式。MVME147可以使用這兩種模式。這位由SYSRESET清除。這些位通過(guò)任何重置設置為1，1。注意，寫(xiě)入REQLEV1,0不會(huì )更改實(shí)際請求者級別，直到MVME147執行以下操作：擁有并釋放VMEbus主控權。這意味著(zhù)有時(shí)，寫(xiě)入REQLEV1,0的值不會(huì )匹配當前請求者級別（請求級別滯后）。在此期間，REQLEV1,0的讀數反映了實(shí)際者級別，而不是寫(xiě)入REQLEV1,0的值。位3將該位設置為1可防止請求者釋放VMEbus。但是，與DWB控制位不同，設置
RNEVER位不會(huì )導致請求者請求VMEbus。清除RNEVER位允許請求者根據其他控制位放棄VMEbus請求者配置寄存器。該位被任何重置。
The SCON status bit is a reflection of the configuration of
header J3. When J3 pins 1 and 2 are connected, enabling the
MVME147 to act as the VMEbus system controller, then SCON
= 1. When J3 pins 1 and 2 are not connected, the MVME147 is
not the VMEbus system controller and SCON = 0.
Bit 1 This bit allows the software to initiate a global reset sequence.
Setting the SRESET bit activates the SYSRESET* signal on the
VMEbus which in turn resets the MVME147. This bit clears
automatically after the reset is complete. This bit is cleared by
any reset.
Bit 2 Setting BRDFAIL to 1 causes the VMEchip to attempt to activate
the SYSFAIL* signal on the VMEbus. The GCSR bit Inhibit
SYSFAIL (ISF), in global register 1, enables the MVME147 to
cause SYSFAIL* to be activated as a result of the state of
BRDFAIL. In addition, when the bit is set, the FAIL LED is lit. (A
watchdog time-out from the PCC also lights the FAIL LED.)
This bit is set by any reset.
Bit 3 The ROBIN bit configures the VMEbus arbitration mode.
ROBIN = 1 forces the round-robin mode. ROBIN = 0 forces the
priority mode. Both modes can be used by the MVME147. This
bit is cleared by SYSRESET. These bits are set to 1, 1 by any reset.
Note that writes to REQLEV1,0 do not change the actual
requester level until the MVME147 goes through the action of
having VMEbus mastership and releasing it. This means that
there are times when the value written into REQLEV1,0 do not
match the current requester level (the request level is lagging).
During such times, reads to REQLEV1,0 reflect the actual
requester level, not the value written into REQLEV1,0.
Bit 3 Setting this bit to 1 prevents the requester from releasing the
VMEbus. However, unlike the DWB control bit, setting the
RNEVER bit does not cause the requester to request the
VMEbus. Clearing the RNEVER bit allows the requester to
relinquish the VMEbus in accordance with the other control bits
of the requester configuration register. This bit is cleared by any
reset.
