DEIF SCM4.1負載單元控制器，SCM4.1使用配置教程
實(shí)用程序中斷向量寄存器提供本地每個(gè)實(shí)用程序都具有唯一向量的CPU中斷。仔細檢查后發(fā)現每個(gè)公用電中斷的級別，如本章中的實(shí)用程序中斷掩碼寄存器部分是與分配的ID相同。這由反映地址行A01-A03的狀態(tài)，即當本地CPU確認中斷到效用向量寄存器的位0-2。在正常運行過(guò)程中訪(fǎng)問(wèn)該寄存器時(shí)CPU讀取周期，位0-2產(chǎn)生寄存器偏移值（即%xxxxx 001）。
DEIF SCM4.1負載單元控制器實(shí)用程序中斷向量寄存器的內容當一個(gè)公用設施中斷時(shí)，不得更改處于活動(dòng)狀態(tài)。實(shí)用程序中斷向量寄存器的下三位是由VMEchip編碼，以唯一標識導致公用事業(yè)中斷請求，如表4-7所示。位3-7 UVB3到UVB7是效用向量基位。寄存器的上五位可通過(guò)以下方式編程：軟件為中提供的矢量提供唯一的基礎確認公用電中斷之一的過(guò)程。這些位通過(guò)任何重置清除。該寄存器用于配置中斷請求中斷器激活以請求中斷VMEbus。三條中斷電平選擇線(xiàn)的編碼如所示表4-8。將非0值寫(xiě)入這三個(gè)位會(huì )導致用于激活相應VMEbus IRQ線(xiàn)路的斷路器。由于中斷器在確認釋放（ROAK）模式下工作，因此中斷請求寄存器為清除，當芯片響應VMEbus中斷確認周期。這些位通過(guò)系統重置。
The utility interrupt vector register provides the local
CPU with a unique vector for each of the utility
interrupts. Close examination reveals that the assigned
level of each of the utility interrupts, as defined in the
Utility Interrupt Mask Register section in this chapter, is
the same as its assigned ID. This is implemented by
reflecting the state of the address lines A01-A03, that
the local CPU drives when it acknowledges an
interrupt, onto bits 0-2 of the utility vector register.
When accessing this register in the course of a normal
CPU read cycle, bit 0-2 yields the register offset value
(which is %xxxxx001).
The contents of the utility interrupt vector register
must not be changed while one of the utility interrupts
is active. The lower three bits of the utility interrupt vector register are
encoded by the VMEchip to uniquely identify the function that
caused the utility interrupt request as shown in Table 4-7.
Bits 3-7 UVB3 through UVB7 are utility vector base bits.
The upper five bits of the register are programmable by
software to provide a unique base for the vector provided in the
course of acknowledging one of the utility interrupts. These bits
are cleared by any reset. This register is used to configure the interrupt request
line that the interrupter activates to request an
interrupt on the VMEbus.
The three interrupt level select lines are encoded as shown in
Table 4-8. Writing a non-0 value to these three bits causes the
interrupter to activate the corresponding VMEbus IRQ line.
Because the interrupter operates in the Release-OnAcknowledge (ROAK) mode, the interrupt request register is
cleared, deactivating the IRQ line when the chip responds to a
VMEbus interrupt acknowledge cycle. These bits are cleared by
SYSRESET.
