UNS0119A-P,V101 3BHE029153R0101勵磁模塊，ABB說(shuō)明書(shū)
VMEbus從接口VMEchip為MVME147。當VMEbus想要訪(fǎng)問(wèn)DRAM或VMEchip控制寄存器，VMEbus映射解碼器選擇VMEchip。對于DRAM訪(fǎng)問(wèn)，VMEchip請求本地總線(xiàn)和獲得主控權后，VMEchip激活適當的信號訪(fǎng)問(wèn)DRAM。DRAM通知VMEchip和當DRAM完成時(shí)，VMEchip通知VMEbus。訪(fǎng)問(wèn)VMEchip不需要掌握本地總線(xiàn)全局控制和狀態(tài)寄存器。
UNS0119A-P,V101 3BHE029153R0101勵磁模塊VMEbus無(wú)法訪(fǎng)問(wèn)
MVME147上除DRAM之外的任何其他資源。通用控制芯片（GCC）GCC是一種CMOS ASIC，設計用于取代16個(gè)PAL和19個(gè)其他PAL先前MVME147單板計算機上的設備。它提供MC68030、VMEchip、PCC、，MVME147上的LANCE和DRAM。同時(shí)保留MVME147的原始功能，GCC降低部分和制造成本和降低功耗。
GCC包括以下功能：? 本地DRAM控制器：–DRAM陣列的控制信號–MPU到DRAM接口–PCC至DRAM接口–噴管至DRAM接口–VMEchip到DRAM接口–用于MPU和PCC到DRAM的本地總線(xiàn)映射解碼器–刷新控制器–字節奇偶校驗生成器/檢查器
? 外部可選內部/外部本地總線(xiàn)仲裁器
? MC68030至MC68882接口邏輯
? 從奇偶校驗和其他錯誤生成局部總線(xiàn)BERR*
? 支持WAITRMC功能
? MC68030到VMEbus映射解碼器
? 其他其他控制邏輯：CIIN*、SCIRST*，異步*SCSI重置因為WD33C93不實(shí)現SCSI總線(xiàn)重置（RST），GCC有單獨的信號來(lái)感應和驅動(dòng)它。
VMEbus Slave Interface
The VMEchip provides the VMEbus slave interface for the
MVME147. When the VMEbus wants to access the DRAM or
VMEchip control registers, the VMEbus map decoder selects the
VMEchip.
For a DRAM access, the VMEchip requests the local bus and after
obtaining mastership, the VMEchip activates the proper signals to
access the DRAM. The DRAM notifies the VMEchip and the
VMEchip notifies the VMEbus when the DRAM has completed.
Mastership of the local bus is not required to access the VMEchip
Global Control and Status Registers. The VMEbus cannot access
any other resources than DRAM on the MVME147. General Control Chip (GCC)
The GCC is a CMOS ASIC designed to replace 16 PALs and 19 other
devices on the previous MVME147 single board computers. It
provides the interface between the MC68030, VMEchip, PCC,
LANCE, and DRAM on the MVME147. While preserving the
original function of the MVME147, the GCC lowers part and
manufacture cost and reduces power consumption.
The GCC includes the following features:
? Local DRAM controller:
– Control signals to DRAM array
– MPU to DRAM interface
– PCC to DRAM interface
– LANCE to DRAM interface
– VMEchip to DRAM interface
– Local bus map decoder for MPU and PCC to DRAM
– Refresh controller
– Byte parity generator/checker
? External selectable internal/external local bus arbiter
? MC68030 to MC68882 interface logic
? Local bus BERR* generation from parity and other errors
? Support for WAITRMC function
? MC68030 to VMEbus map decoder
? Other miscellaneous control logic: CIIN*, SCIRST*,
ASYNCH*
SCSI Reset
Because the WD33C93 does not implement SCSI bus Reset (RST),
the GCC has separate signals to sense and drive it.
