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1786-RPFPXLB模塊

作者:xqt 發(fā)布時(shí)間:2022-07-06 15:26:52 次瀏覽

1786-RPFPXLB模塊,A-B英文使用說(shuō)明串行通信接口MVME172LX使用兩個(gè)Zilog Z85230串行端口控制器來(lái)實(shí)現四個(gè)串行通信接口。每個(gè)接口支持CT、DCD、RTS和DTR控制信號,以及TXD和RXD發(fā)送/接收數據信號。因為串行時(shí)鐘是在MVME172LX實(shí)現中省略了串行通信嚴格異步。MVME172LX硬件支持串行波特率速率為110b/s至38.4Kb/s。Z85230在中斷確認期間

1786-RPFPXLB模塊,A-B英文使用說(shuō)明

串行通信接口MVME172LX使用兩個(gè)Zilog Z85230串行端口控制器來(lái)實(shí)現四個(gè)串行通信接口。每個(gè)接口支持CT、DCD、RTS和DTR控制信號,以及TXD和RXD發(fā)送/接收數據信號。因為串行時(shí)鐘是在MVME172LX實(shí)現中省略了串行通信嚴格異步。MVME172LX硬件支持串行波特率速率為110b/s至38.4Kb/s。Z85230在中斷確認期間提供中斷矢量周期。該向量根據中斷請求電平通過(guò)MC2chip編程。

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1786-RPFPXLB模塊參考本章中列出的Z85230數據表和MC2chipMVME172 VME嵌入式控制器的編程模型程序員參考指南,供參考。Z85230s作為DTE(數據終端設備)與EIA232-D信號電平連接。四個(gè)串行端口路由到四個(gè)RJ-45MVME172LX前面板上的連接器。IP接口MVME172LX上最多可以安裝兩個(gè)IP模塊。IPs和MVME172LX之間的接口是IndustryPack接口控制器(IP2)ASIC。兩個(gè)3M公司提供IPs接入連接器位于MVME172LX前面板后面。請參閱MVME172 VME嵌入式控制器中的IP2章節IP接口詳細功能的程序員參考指南。以太網(wǎng)接口MVME172LX使用Intel 82596CA LAN協(xié)處理器實(shí)現以太網(wǎng)收發(fā)器接口。82596CA訪(fǎng)問(wèn)本地RAM使用DMA操作來(lái)執行其正常功能。因為82596CA具有較小的內部緩沖區,VMEbus具有未定義的延遲期,如果DMA編程為訪(fǎng)問(wèn)VMEbus。因此,82596CA不應編程訪(fǎng)問(wèn)VMEbus。每個(gè)具有以太網(wǎng)接口的MVME172LX都分配了一個(gè)以太網(wǎng)車(chē)站地址。地址是$08003E2xxxxx,其中xxxxx是唯一的分配給電路板的5位數字(即,每個(gè)MVME172LX都有一個(gè)xxxxx的值不同)。每個(gè)電路板都有一個(gè)以太網(wǎng)站地址,顯示在標簽上至VMEbus P2連接器。此外,包以太網(wǎng)地址存儲在BBRAM的配置區域中。那個(gè)is,08003E2xxxxx存儲在BBRAM中。前四個(gè)字節(08003E2x)讀取為$FFFC1F2C;下兩個(gè)字節(xxxx)在以下位置讀?。?FFFC1F30。MVME172調試器能夠檢索或設置以太網(wǎng)地址。

Serial Communications Interface

The MVME172LX uses two Zilog Z85230 serial port controllers to

implement the four serial communications interfaces. Each interface

supports CTS, DCD, RTS, and DTR control signals, as well as the TXD

and RXD transmit/receive data signals. Because the serial clocks are

omitted in the MVME172LX implementation, serial communications are

strictly asynchronous. The MVME172LX hardware supports serial baud

rates of 110b/s to 38.4Kb/s.

The Z85230 supplies an interrupt vector during interrupt acknowledge

cycles. The vector is modified based upon the interrupt source within the

Z85230. Interrupt request levels are programmed via the MC2chip. Refer

to the Z85230 data sheet listed in this chapter, and to the MC2chip

Programming Model in the MVME172 VME Embedded Controller

Programmer’s Reference Guide, for information.

The Z85230s are interfaced as DTE (data terminal equipment) with EIA232-D signal levels. The four serial ports are routed to four RJ-45

connectors on the MVME172LX front panel.

IP Interfaces

Up to two IP modules may be installed on the MVME172LX as an option.

The interface between the IPs and MVME172LX is the IndustryPack

Interface Controller (IP2) ASIC. Access to the IPs is provided by two 3M

connectors located behind the MVME172LX front panel. Refer to the

chapter on the IP2 in the MVME172 VME Embedded Controller

Programmer’s Reference Guide for detailed features of the IP interface. Ethernet Interface

The MVME172LX uses the Intel 82596CA LAN coprocessor to

implement the Ethernet transceiver interface. The 82596CA accesses local

RAM using DMA operations to perform its normal functions. Because the

82596CA has small internal buffers and the VMEbus has an undefined

latency period, buffer overrun may occur if the DMA is programmed to

access the VMEbus. Therefore, the 82596CA should not be programmed

to access the VMEbus.

Every MVME172LX that has an Ethernet interface is assigned an Ethernet

Station Address. The address is $08003E2xxxxx where xxxxx is the unique

5-nibble number assigned to the board (i.e., every MVME172LX has a

different value for xxxxx).

Each board has an Ethernet Station Address displayed on a label attached

to the VMEbus P2 connector. In addition, the six bytes including the

Ethernet address are stored in the configuration area of the BBRAM. That

is, 08003E2xxxxx is stored in the BBRAM. The upper four bytes

(08003E2x) are read at $FFFC1F2C; the lower two bytes (xxxx) are read at

$FFFC1F30. The MVME172 debugger has the capability to retrieve or set

the Ethernet address.


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