1C31129G03功率模塊，EMERSON配置說(shuō)明
正常地址范圍響應正常地址的設備的內存映射范圍如下表所示。正常地址范圍為由本地總線(xiàn)上的傳輸類(lèi)型（TT）信號定義。上MVME177，傳輸類(lèi)型0、1和2定義正常地址范圍表3-1。本地總線(xiàn)內存映射，是從$00000000開(kāi)始的整個(gè)映射到$FFFFFF。地圖的許多區域是用戶(hù)可編程的，并且建議的用途如表所示。
1C31129G03功率模塊緩存抑制功能為可在MMU中編程。車(chē)載輸入/輸出空間必須標記緩存禁止并在其頁(yè)表中序列化。第3-6頁(yè)的表3-2進(jìn)一步定義了本地輸入/輸出的映射設備。1.Flash/EPROM設備的價(jià)格為$FF800000至$FFBFFFFF，如果ROM0位在VMEchip2 EPROM控制寄存器為高電平（ROM0=1）。這個(gè)ROM0位位于地址$FFF40030位20。ROM0設置為1每次重置后。必須先清除ROM0位，然后再清除其他位可以在此范圍內映射資源（DRAM或SRAM）（$00000000至$003FFFFF）。VMEchip2和DRAM映射解碼器被本地總線(xiàn)重置禁用。MVME177上，閃存/EPROM內存映射為硬件默認情況下，通過(guò)VMEchip2.2。該區域可由用戶(hù)編程。建議使用如所示桌子。DRAM解碼器在MCECC芯片中編程，本地到VMEbus解碼器在VMEchip2。3、尺寸為近似值。4.緩存抑制取決于映射區域中的設備。5、該區域未解碼。如果訪(fǎng)問(wèn)了這些位置本地總線(xiàn)計時(shí)器啟用，循環(huán)超時(shí)，并通過(guò)以下方式終止茶的信號。SRAM在MVME177上有可選的備用電池。下表重點(diǎn)介紹了本地總線(xiàn)主內存映射。有關(guān)寄存器位的完整描述，請參閱數據特定芯片的表。有關(guān)更詳細的內存映射，請參閱到以下詳細的外圍設備內存映射。應使用字節讀取來(lái)讀取中斷向量。這些當中斷未掛起時(shí)，位置不響應。如果總線(xiàn)計時(shí)器已啟用，訪(fǎng)問(wèn)超時(shí)并終止TEA信號。
Normal Address Range
The memory map of devices that respond to the normal address
range is shown in the following tables. The normal address range is
defined by the Transfer Type (TT) signals on the local bus. On the
MVME177, Transfer Types 0, 1, and 2 define the normal address
range.
Table 3-1. Local Bus Memory Map, is the entire map from $00000000
to $FFFFFFFF. Many areas of the map are user-programmable, and
suggested uses are shown in the table. The cache inhibit function is
programmable in the MMUs. The onboard I/O space must be
marked cache inhibit and serialized in its page table.
Table 3-2 on page 3-6 further defines the map for the local I/O
devices.1. Flash/EPROM devices appear at $FF800000 through $FFBFFFFF,
and also appear at $00000000 through $003FFFFF if the ROM0 bit in
the VMEchip2 EPROM control register is high (ROM0 = 1). The
ROM0 bit is located at address $FFF40030 bit 20. ROM0 is set to 1
after each reset. The ROM0 bit must be cleared before other
resources (DRAM or SRAM) can be mapped in this range
($00000000 through $003FFFFF). The VMEchip2 and DRAM map
decoders are disabled by a local bus reset.
On the MVME177, the Flash/EPROM memory is mapped at
$00000000 through $003FFFFF by hardware default through the
VMEchip2.2. This area is user-programmable. The suggested use is shown in
the table. The DRAM decoder is programmed in the MCECC chip,
and the local-to-VMEbus decoders are programmed in the
VMEchip2.
3. Size is approximate.
4. Cache inhibit depends on devices in area mapped.
5. This area is not decoded. If these locations are accessed and the
local bus timer is enabled, the cycle times out and is terminated by
a TEA signal.
6. The SRAM has optional battery backup on the MVME177.
The following table focuses on the Local I/O Devices portion of the
local bus Main Memory Map. For a complete description of the register bits, refer to the data
sheet for the specific chip. For a more detailed memory map, refer
to the following detailed peripheral device memory maps. Byte reads should be used to read the interrupt vector. These
locations do not respond when an interrupt is not pending. If the
local bus timer is enabled, the access times out and terminates by a
TEA signal.
