DEIF PCM4.3控制通訊板，PCM4.3配置說(shuō)明
應始終清除SLVD16。將SLVD16設置為1將VMEchip從設備配置為僅提供D08（EO）和D16數據傳輸能力。通常在本地總線(xiàn)只有16位寬。將SLVD16位清除為0配置VMEchip從機提供D08（EO）、D16和D32/UAT數據傳輸能力。該位由SYSRESET清除。位5設置SLVWP位加速VMEbus寫(xiě)入板載DRAM。
DEIF PCM4.3控制通訊板當設置SLVWP（從寫(xiě)過(guò)賬）時(shí)，VMEbus板載DRAM的寫(xiě)入周期由VMEchip，然后將數據寫(xiě)入DRAM。這允許VMEbus主機快速結束其循環(huán)，放置VMEchip完成板載寫(xiě)入的負擔DRAM本身。該位由SYSRESET清除。位7將SLVEN設置為1使其他VMEbus主機能夠訪(fǎng)問(wèn)MVME147機載DRAM。該位由SYSRESET清除。將ARBTO設置為1將啟用VMEbus仲裁計時(shí)器。這個(gè)如果未激活，VMEbus仲裁計時(shí)器將激活BBSY*MVME147仲裁器發(fā)出總線(xiàn)授權后410μs內。這個(gè)計時(shí)器根據VMEbus中的規定停用BBSY*規格這導致仲裁人對任何未決案件進(jìn)行仲裁請求公共汽車(chē)。該位由SYSRESET設置為1。該寄存器允許軟件配置VMEbus主機必須使用的地址修飾符代碼訪(fǎng)問(wèn)機載DRAM。寄存器的8位分為三組。至少一個(gè)位在每個(gè)組中必須設置，否則地址忽略主控形狀使用的修飾符。地址位7位6位5位4位3位2位1位0FFFE200B超級用戶(hù)擴展STND短塊PRGRM數據位0-2這三個(gè)位構成配置從機的第一組AM代碼。將任何位設置為1使從機能夠響應以下示例中所述的循環(huán)。筆記不應設置塊。這些位通過(guò)系統重置。位3-5這三個(gè)位構成第二組。將任何位設置為1使從機能夠響應中所述的周期示例如下。這些位由SYSRESET清除。位6-7這兩個(gè)位形成第三組。將任何位設置為1使從屬設備能夠響應中所述的周期
SLVD16 should always be cleared. Setting SLVD16 to 1
configures the VMEchip slave to provide only D08 (EO) and
D16 data transfer capabilities. It is typically set when the local
bus is only 16 bits wide. Clearing the SLVD16 bit to 0 configures
the VMEchip slave to provide the D08 (EO), D16, and D32/UAT
data transfer capabilities. This bit is cleared by SYSRESET.
Bit 5 Setting the SLVWP bit speeds up VMEbus writes to the onboard
DRAM. When SLVWP (slave write posting) is set, VMEbus
write cycles to the onboard DRAM are acknowledged by the
VMEchip before the data has been written into the DRAM. This
allows the VMEbus master to end its cycle quickly, placing the
burden on the VMEchip to complete the write to onboard
DRAM on its own. This bit is cleared by SYSRESET.
Bit 7 Setting SLVEN to 1 enables other VMEbus masters to access the
MVME147 onboard DRAM. This bit is cleared by SYSRESET. Setting ARBTO to 1 enables the VMEbus arbitration timer. The
VMEbus arbitration timer activates BBSY* if it is not activated
within 410 μs after the MVME147 arbiter issues a bus grant. The
timer deactivates BBSY* as specified in the VMEbus
specification. This causes the arbiter to arbitrate any pending
requests for the bus. This bit is set to 1 by SYSRESET. This register allows software to configure which
address modifier codes the VMEbus masters must use
to access the onboard DRAM. The 8 bits of the register
are organized into three groups. At least one of the bits
in each group must be set, otherwise the address
modifier used by the master is ignored.
ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FFFE200B SUPER USER EXTED STND SHORT BLOCK PRGRM DATA
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 0-2 These three bits form the first group which configures the slave
AM code. Setting any of the bits to 1 enables the slave to
respond to cycles as described in the example below. Note
BLOCK should never be set. These bits are cleared by
SYSRESET.
