BENTLY 330108-91-05模塊本章提供了以下方面的框圖級描述：MVME177模塊。功能描述提供了模塊概述，然后詳細描述模塊的幾個(gè)模塊。MVME177的框圖如第4-3頁(yè)圖4-1所示。MVME177其他模塊的說(shuō)明，包括ASIC和外圍芯片中的可編程寄存器是在單板計算機程序員參考指南中給出。有關(guān)MVME177的其余功能描述
BENTLY 330108-91-05模塊請參閱單元MVME177功能描述MVME177是一種高功能VMEbus單板圍繞MC68060芯片設計的計算機。MVME177具有：? 4/8/16/32/64/128/256MB動(dòng)態(tài)RAM? SCSI大容量存儲接口? 四個(gè)串行端口? 一個(gè)并行端口? 以太網(wǎng)收發(fā)器接口數據總線(xiàn)結構MVME177上的本地數據總線(xiàn)是32位同步總線(xiàn)它基于MC68060總線(xiàn)，支持突發(fā)傳輸和窺探。各種本地總線(xiàn)主設備和從設備使用本地總線(xiàn)進(jìn)行通信。本地總線(xiàn)由優(yōu)先級仲裁類(lèi)型仲裁器和本地總線(xiàn)主節點(diǎn)的優(yōu)先級從高到低最低為：? 82596CA局域網(wǎng)CD2401串行（通過(guò)PCCCip2）? 53C710 SCSI? VME總線(xiàn) 微處理器在一般情況下，任何主機都可以訪(fǎng)問(wèn)任何從機；但是，不是所有組合都通過(guò)常識測試。參考單個(gè)板機程序員參考指南和用戶(hù)的每個(gè)設備的確定指南：? 端口大小? 數據總線(xiàn)連接? 訪(fǎng)問(wèn)設備時(shí)適用的任何限制
Introduction
This chapter provides a block diagram level description for the
MVME177 module. The functional description provides an
overview of the module, followed by a detailed description of
several blocks of the module. The block diagram of the MVME177
is shown in Figure 4-1 on page 4-3.
Descriptions of the other blocks of the MVME177, including
programmable registers in the ASICs and peripheral chips, are
given in the Single Board Computers Programmer's Reference Guide.
Refer to it for the rest of the functional description of the MVME177
module.
MVME177 Functional Description
The MVME177 is a high functionality VMEbus single board
computer designed around the MC68060 chip. The MVME177 has:
? 4/8/16/32/64/128/256MB of dynamic RAM
? SCSI mass storage interface
? Four serial ports
? One parallel port
? Ethernet transceiver interface
Data Bus Structure
The local data bus on the MVME177 is a 32-bit synchronous bus
that is based on the MC68060 bus, and supports burst transfers and
snooping. The various local bus master and slave devices use the local bus to communicate. The local bus is arbitrated by priority
type arbiter and the priority of the local bus masters from highest to
lowest is:
? 82596CA LAN
? CD2401 serial (through the PCCchip2)
? 53C710 SCSI
? VMEbus
? MPU
In the general case, any master can access any slave; however, not
all combinations pass the common sense test. Refer to the Single
Board Computers Programmer's Reference Guide and to the user's
guide for each device to determine:
? Port size
? Data bus connection
? Any restrictions that apply when accessing the device
