BENTLY 330130-080-00-00位置監測器
MC68060微處理器是MVME177。超標量MC68060處理器具有：? 兩個(gè)兼容MC68040的CPU integer內核? MC68040兼容浮點(diǎn)核? 獨立8KB指令和操作數數據緩存? MC68040兼容分頁(yè)內存管理單元? 總線(xiàn)控制器處理器位于PGA插槽中。其時(shí)鐘速度為50 MHz（對于-00x型號）和60 MHz（適用于-01x型號）。請注意，本地處理器總線(xiàn)的運行速度只有處理器速度的一半。請參閱有關(guān)更多信息，請參閱MC68060用戶(hù)手冊。
BENTLY 330130-080-00-00位置監測器閃存和EPROM閃存MVME177包括四個(gè)28F008SA閃存設備。這個(gè)閃存設備提供4MB ROM，地址為FF800000美元-$FFBFFFFF。閃存被組織為一個(gè)32位組，用于32位從處理器執行代碼。例如，閃光燈可能是用于板載調試器固件（177Bug），該固件將從輸入/輸出資源下載，例如：? 以太網(wǎng)? SCSI? 串行端口，或? VMEbus當閃存與EPROM一起使用時(shí)，其頂部或底部2MB閃存在安裝后的第二個(gè)2MB內存空間中可用EPROM。見(jiàn)下表4-1。由于只使用1M x 8位閃存芯片，因此不需要用戶(hù)配置跳線(xiàn)選擇塊來(lái)選擇閃存芯片大小閃存設備的內存映射由VMEchip2專(zhuān)用集成電路。32位寬閃存可以支持：
? 8位? 16位，和? 32位訪(fǎng)問(wèn)閃存寫(xiě)保護可通過(guò)VMEchip2編程GPIO寄存器。Flash的地址圖位置為$000000如果FLASHJP跳線(xiàn)（J8）在，則在本地重置時(shí)通過(guò)3FFFFF，提供全閃光模式。在混合EPROM/閃存中模式下，在20萬(wàn)美元到20萬(wàn)美元的地址可以訪(fǎng)問(wèn)一半的閃存$3FFFFF，取決于VMEchip2 GPIO2位的條件。因為MVME177使用1M x 8位閃存設備和沒(méi)有下載ROM的EPROM，軟件編程VMEchip2 ROM0和REV EROM位正確，以便通電后，閃存/EPROM出現在地址$0處。
MC68060 MPU
The MC68060 microprocessor is the main processor for the
MVME177. The superscalar MC68060 processor has:
? Two MC68040-compatible CPU integer cores
? MC68040-compatible floating point core
? Independent 8KB instruction and operand data caches
? MC68040-compatible paged memory management unit
? A bus controller
The processor is in a PGA socket. Its clock speed is 50 MHz (for the
-00x models), and 60 MHz (for the -01x models). Note that the local
processor bus runs at only half the processor speed. Refer to the
MC68060 user's manual for more information.
Flash Memory and EPROM
Flash Memory
The MVME177 includes four 28F008SA Flash memory devices. The
Flash devices provide 4MB of ROM at address $FF800000-
$FFBFFFFF. The Flash is organized as one 32-bit bank for 32-bit
code execution from the processor. The Flash could, for instance, be
used for the onboard debugger firmware (177Bug) which would be
downloaded from I/O resources such as:
? Ethernet
? SCSI
? A serial port, or
? The VMEbus
When Flash is used with EPROM, either the top or bottom 2MB of
Flash is available in the second 2MB of memory space after the
EPROM. Refer to Table 4-1 below. Because only 1M x 8-bit Flash chips are used, there is no userconfigured jumper selection block required to pick the Flash chip
size.
The memory map for the Flash devices is controlled by the
VMEchip2 ASIC. The 32-bit wide Flash can support:
? 8 bit
? 16 bit, and
? 32 bit access
Flash write protection is programmable through the VMEchip2
GPIO register. The address map location of Flash is at $000000
through $3FFFFF at local reset if the FLASHJP jumper (J8) is in,
providing for the all-Flash mode. In the mixed EPROM/Flash
mode, half of the Flash is accessable at addresses $200000 through
$3FFFFF, depending on the condition of the VMEchip2 GPIO2 bit.
Because the MVME177 uses 1M x 8-bit Flash memory devices and
EPROMs with no download ROM, the software programs the
VMEchip2 ROM0 and REV EROM bits properly so that the
Flash/EPROM appears at address $0 after powerup.
